Predicated vector load micro-operation

A method comprising:

• controlling issuing of micro-operations, decoded from instructions, to processing circuitry, where the controlling of issuing is based on whether operands of the micro-operations meet an availability condition, and the processing circuitry comprises memory access circuitry to control issuing of memory access requests;
• and
• in response to a predicated vector load micro-operation specifying a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses derived from the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive, when the predicated vector load micro-operation is a predetermined type of predicated vector load micro-operation:
• issuing the predetermined type of predicated vector load micro-operation to the processing circuitry before the predicate operand is determined to meet the availability condition;
• determining, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition;
• and
• in response to determining that the predetermined condition is unsatisfied for the predetermined type of predicated vector load micro-operation, performing a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register.

A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:

• processing circuitry to perform data processing in response to micro-operations decoded from instructions, the processing circuitry comprising memory access circuitry to control issuing of memory access requests;
• and
• issue circuitry to control issuing of the micro-operations to the processing circuitry based on whether operands of the micro-operations meet an availability condition;
• in which:
• in response to a predicated vector load micro-operation specifying a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive:
• when the predicated vector load micro-operation is a predetermined type of predicated vector load micro-operation, the issue circuitry is capable of issuing the predetermined type of predicated vector load micro-operation to the processing circuitry before the predicate operand is determined to meet the availability condition;
• and
• when the predetermined type of predicated vector load micro-operation is issued to the processing circuitry before the predicate operand meets the availability condition, the memory access circuitry is configured to:
• determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition;
• and
• in response to determining that the predetermined condition is unsatisfied for the predetermined type of predicated vector load micro-operation, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register.