Pedestal-based pocket integration process for embedded memory

A device comprising:

• a first region comprising:
• a trench interconnect extending along a first direction within a first level;
• a second level above the first level, the second level comprising:
• a plurality of ferroelectric memory devices laterally spaced apart above the trench interconnect;
• an electrode structure comprising a first sidewall, the electrode structure coupled between a respective ferroelectric memory device in the plurality of ferroelectric memory devices and the trench interconnect;
• and
• an encapsulation layer on second sidewall of individual ones of the plurality of ferroelectric memory devices, wherein an outer third sidewall of the encapsulation layer is substantially aligned with the first sidewall;
• a via electrode on individual ones of the plurality of ferroelectric memory devices;
• and
• a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
• one or more second conductive interconnects within the first level;
• an etch stop layer comprising a dielectric material in the second level;
• a plurality of metal lines above the etch stop layer, the plurality of metal lines in the second level;
• and
• a via structure coupling a metal line in the plurality of metal lines with a second conductive interconnect in the one or more second conductive interconnects, wherein the via structure is in the second level and wherein an uppermost surface of the via electrode is co-planar with an uppermost surface of the plurality of metal lines.

A method of fabricating a device structure, the method comprising:

• forming a plurality of conductive interconnects in a dielectric in a memory region and one or more conductive interconnects in a logic region;
• depositing an etch stop layer on the dielectric and on the plurality of conductive interconnects and on the one or more conductive interconnects;
• etching to remove the etch stop layer from a memory region but not from a logic region;
• depositing an electrode material on the plurality of conductive interconnects in the memory region and on the etch stop layer in the logic region;
• depositing a material layer stack on the electrode material;
• forming a plurality of memory devices by etching the material layer stack, wherein the etching forms an individual memory device in the plurality of memory devices above a respective conductive interconnect in the plurality of conductive interconnects in the memory region;
• depositing an encapsulation layer on the plurality of memory devices and on the electrode material;
• forming a mask on the encapsulating layer and patterning the encapsulating layer and electrode material, wherein the mask is above an individual memory device in the plurality of memory devices;
• blanket depositing a dielectric layer;
• forming a plurality of openings in the dielectric layer, the plurality of openings exposing a respective memory device in the plurality of memory devices;
• forming a respective via electrode in a respective opening in the plurality of openings by depositing a conductive material in the plurality of openings;
• forming one or more openings in the dielectric layer and in the encapsulation layer, the one or more openings exposing the one or more conductive interconnects in the logic region;
• and
• forming an interconnect via in a respective one or more openings and a metal line on a respective interconnect via by depositing the conductive material in the one or more openings.