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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCHIA-WEI HUANG, WEI-JHIH WANG, CHENG-CHENG KUO, YUAN-YAO CHANG
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The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.
A wafer, comprising:
A method for manufacturing a test circuit, comprising:
A method for testing a wafer, the wafer including a die, a scribe line adjacent to the die, and a test circuit in the scribe line, the test circuit including a first switch coupled to a first contact pad, a second switch coupled to a second contact pad, and a third switch coupled to a third contact pad and a fourth contact pad, the method comprising:
Dependencies are inferred from the claim text.