Semiconductor device

A semiconductor device, comprising:

• a first active pattern and a second active pattern on a substrate;
• a device isolation layer filling a trench between the first and second active patterns;
• a first source/drain pattern on the first active pattern;
• a second source/drain pattern on the second active pattern;
• a first channel pattern connected to the first source/drain pattern;
• a second channel pattern connected to the second source/drain pattern;
• and
• a gate electrode extending to cross the first and second channel patterns, the gate electrode comprises a first electrode portion on the first active pattern and a second electrode portion on the second active pattern,
• wherein the first electrode portion comprises a first metal pattern covering the first active pattern and a second metal pattern on the first metal pattern,
• the second electrode portion comprises a third metal pattern covering the second active pattern and a fourth metal pattern on the third metal pattern,
• the first metal pattern comprises a first line portion, a first vertical portion, and a protruding portion, the first line portion extending parallel to a top surface of the device isolation layer, the first vertical portion extending vertically from the first line portion, and the protruding portion protruding from the first line portion toward the third metal pattern, and
• the third metal pattern comprises a second line portion, a second vertical portion, and a stepwise portion, the second line portion extending parallel to the top surface of the device isolation layer, the stepwise portion covering the protruding portion, and the second vertical portion extending vertically from the stepwise portion and vertically overlapping the protruding portion.

A semiconductor device, comprising:

• a substrate including a first active region, a second active region adjacent to the first active region in a first direction, and a trench between the first active region and the second active region;
• a device isolation layer filling the trench;
• a first active pattern on the first active region;
• a second active pattern on the second active region;
• a first source/drain pattern on the first active pattern;
• a second source/drain pattern on the second active pattern;
• a first channel pattern connected to the first source/drain pattern, the first channel pattern comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern vertically spaced apart from each other;
• a second channel pattern connected to the second source/drain pattern, the second channel pattern comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern which are vertically spaced apart from each other;
• a gate electrode extending in the first direction to cross the first and second channel patterns, the gate electrode comprising a first electrode portion on the first active region, and a second electrode portion on the second active region, the gate electrode comprising, for at least one of the first or second channel patterns, a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, a third portion between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion on the third semiconductor pattern;
• a gate insulating layer interposed between the first channel pattern and the gate electrode and between the second channel pattern and the gate electrode;
• a gate spacer on a side surface of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• a first interlayer insulating layer on the gate capping pattern;
• active contacts penetrating the first interlayer insulating layer and coupled to the first and second source/drain patterns, respectively;
• a gate contact penetrating the first interlayer insulating layer and coupled to the gate electrode;
• a second interlayer insulating layer on the first interlayer insulating layer;
• a first metal layer in the second interlayer insulating layer, the first metal layer comprising lower interconnection lines electrically connected to the active contacts and the gate contact, respectively;
• a third interlayer insulating layer on the second interlayer insulating layer;
• and
• a second metal layer provided in the third interlayer insulating layer, the second metal layer comprising upper interconnection lines electrically connected to the lower interconnection lines, respectively,
• wherein the first electrode portion comprises a first metal pattern covering the first active pattern and a second metal pattern on the first metal pattern,
• the second electrode portion comprises a third metal pattern covering the second active pattern and a fourth metal pattern on the third metal pattern,
• the first metal pattern comprises a first line portion and first vertical portion, the first line portion extending parallel to a top surface of the device isolation layer, and the first vertical portion extending vertically from the first line portion,
• the third metal pattern comprises a second line portion and a second vertical portion, the second line portion extending parallel to the top surface of the device isolation layer, and the second vertical portion extending vertically from the second line portion, and
• the first vertical portion and the second vertical portion are in contact with each other.