Vertical field-effect transistor, method for producing a vertical field-effect transistor and component having vertical field-effect transistors

A vertical field-effect transistor, comprising:

• a first semiconductor layer, which has a p-type conductivity, situated on or over a drift region;
• a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure;
• a source-drain electrode, which is electroconductively connected to the III-V-heterostructure;
• and
• a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode;
• and
• at least a region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

A component, comprising:

• a first vertical field-effect transistor and a second vertical field-effect transistor, each of which including:
• a first semiconductor layer, which has a p-type conductivity, on or over a drift region,
• a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-hetero structure, and
• a source-drain electrode, which is electroconductively connected to the III-V-heterostructure;
• a contact structure at least partially on or over the drift region, the contact structure being formed laterally between the groove structure of the first vertical field-effect transistor and the groove structure of the second vertical field-effect transistor and being electroconductively connected to the source-drain electrode of at least one of the first and second vertical field-effect transistors, at least a region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

A method for producing a vertical field-effect transistor, the method comprising:

• forming a first semiconductor layer, which has a p-type conductivity, on or over a drift region;
• forming a groove structure which penetrates the first semiconductor layer vertically, the groove structure being formed with at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure;
• forming a source-drain electrode, which is electroconductively connected to the III-V-heterostructure;
• and
• forming a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode;
• wherein at least a region lying vertically between the contact structure and the drift region remaining free of the first semiconductor layer.