Semiconductor die including stress-resistant bonding structures and methods of forming the same

A semiconductor structure comprising a semiconductor die, wherein:

• the semiconductor die comprises dielectric material layers embedding metal interconnect structures and a bump structure that includes a bonding bump portion and a bump via portion extending toward the metal interconnect structures;
• a solder material portion is attached to the bump structure;
• and
• a vertical axis passing through a geometrical center of the solder material portion is laterally offset from a vertical axis passing through a geometrical center of the bump via portion.

A method of forming a semiconductor structure including a semiconductor die, comprising:

• forming dielectric material layers and metal interconnect structures over a semiconductor substrate, wherein the dielectric material layers comprise a pad-level dielectric material layer;
• forming a connection pad-and-via structure over the dielectric material layers, wherein the connection pad-and-via structure comprises a connection via portion that extends through the pad-level dielectric material layer and a pad portion that overlies the pad-level dielectric material layer;
• forming a bump-level dielectric material layer over the connection pad-and-via structure;
• and
• forming a bump structure on the bump-level dielectric material layer, wherein the bump structure comprises a bump via portion extending through the bump-level dielectric material layer and contacting the pad portion and a bonding bump portion overlying the bump-level dielectric material layer, wherein a vertical axis passing through a geometrical center of the bump via portion is laterally offset from a vertical axis passing through a geometric center of the connection via portion of the connection pad-and-via structure.