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US 2023/0065769 A1Published application
Memory device, semiconductor die, and method of fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Jung Yu, Pin-Cheng Hsu
Life of this patent
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Abstract
A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
Claims20
A memory device, comprising:
- a transistor, comprising:
- a first gate;
- a second gate disposed above the first gate;
- a first channel layer disposed between the first gate and the second gate;
- a first source electrode and a first drain electrode disposed at opposite sides of the first channel layer;
- a third gate disposed above the second gate, wherein the third gate is electrically connected to the first gate and the second gate;
- a second channel layer disposed between the second gate and the third gate;
- a second source electrode and a second drain electrode disposed at opposite sides of the second channel layer, wherein the first source electrode is electrically connected to the second source electrode, and the first drain electrode is electrically connected to the second drain electrode;
- and
- a memory cell electrically connected to the first drain electrode and second drain electrode.
7 more elements
A semiconductor die, comprising:
- a semiconductor substrate;
- an interconnect structure disposed over the semiconductor substrate, the interconnect structure comprising an embedded memory cell array, the embedded memory cell array comprising word lines, bit lines, source lines, and memory devices, at least one of the memory devices comprising a transistor and a memory cell electrically connected to the transistor, and at least one of the transistors comprising:
- a bottom gate;
- a top gate disposed above the bottom gate;
- a middle gate disposed between the bottom gate and the top gate;
- a first channel layer disposed between the bottom gate and the middle gate;
- a first source electrode and a first drain electrode disposed at opposite sides of the first channel layer;
- a second channel layer disposed between the middle gate and the top gate;
- and
- a second source electrode and a second drain electrode disposed at opposite sides of the second channel layer, wherein the bottom gate, the middle gate and the top gate are electrically connected to one of the word lines, the first source electrode and the second source electrode are electrically connected to one of the source lines, a first terminal of the memory cell is electrically connected to the first drain electrode and the second drain electrode, and a second terminal of the memory cell is electrically connected to one of the bit lines.
7 more elements
A method, comprising:
- forming a first gate;
- forming a first gate insulating layer over the first gate;
- forming a first channel layer, a first source electrode and a first source electrode over the first gate insulating layer;
- forming a second gate insulating layer over the first channel layer, the first source electrode and the first source electrode;
- forming a second gate over the second gate insulating layer;
- forming a third gate insulating layer over the second gate;
- forming a second channel layer, a second source electrode and a second drain electrode over the third gate insulating layer;
- forming a fourth gate insulating layer over the second channel layer, the second source electrode and the second drain electrode;
- and
- forming a third gate over the fourth gate insulating layer, wherein the first gate, the second gate and the third gate are electrically connected to one another, the first source electrode and the second source electrode are electrically connected to each other, and the first drain electrode and the second drain electrode are electrically connected to each other.
7 more elements
Dependencies are inferred from the claim text.