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US 2023/0065715 A1Published application
Stacked complementary field effect transistors
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, HUIMEI ZHOU, MIAOMIAO WANG, Alexander Reznicek
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Abstract
A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.
Claims20
A CFET structure (complementary field effect transistor) comprising:
- a first transistor disposed above a second transistor;
- and
- a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.
A CFET structure (complementary field effect transistor) comprising:
- a first transistor disposed above a second transistor;
- and
- a pair of first source/drain regions of the first transistor disposed above a pair of second source/drain regions of the second transistor, wherein each of the pair of second source/drain regions comprises a recessed notch beneath a corresponding first source-drain region.
A method of fabricating a semiconductor device, the method comprising:
- forming stacked sets of field effect transistor channel elements;
- forming first source/drain regions for a first transistor;
- forming a recessed notch in an upper surface of the first source/drain region;
- forming an isolation layer in the notch and above the first source/drain regions;
- and
- forming second source/drain regions for a second transistor above the notch.
3 more elements
Dependencies are inferred from the claim text.