US 2023/0065666 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorYoichi MINEMURA

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Abstract

According to one embodiment, a semiconductor memory device includes first conductive layers stacked on a substrate at a first pitch, second conductive layers stacked on the substrate at a second pitch, and third conductive layers stacked on the substrate at a third pitch. The third conductive layers are between the substrate and the second conductive layers in a first direction. A semiconductor layer extends in the first direction through the first conductive layers, the second conductive layers, and the third conductive layers. The semiconductor layer has a first portion facing the first conductive layers and the second conductive layers and a second portion facing the third conductive layers. The second pitch is greater than the first pitch and the third pitch.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a plurality of first conductive layers stacked on a substrate along a first direction at a first pitch;
a plurality of second conductive layers stacked on the substrate along the first direction at a second pitch, the plurality of second conductive layers being between the substrate and the plurality of first conductive layers in the first direction;
a plurality of third conductive layers stacked on the substrate along the first direction at a third pitch, the plurality of third conductive layers being between the substrate and the plurality of second conductive layers in the first direction;
and
a semiconductor layer extending in the first direction through the first conductive layers, the second conductive layers, and the third conductive layers, wherein
the semiconductor layer has a first portion facing the first conductive layers and the second conductive layers and a second portion facing the third conductive layers, and
the second pitch is greater than the first pitch and the third pitch.

4 more elements

A semiconductor memory device, comprising:

a plurality of first conductive layers stacked on a substrate along a first direction at a first pitch;
a plurality of second conductive layers stacked on the substrate along the first direction at a second pitch, the plurality of second conductive layers being between the substrate and the plurality of first conductive layers in the first direction;
a plurality of third conductive layers stacked on the substrate along the first direction, the plurality of third conductive layers being between the substrate and the plurality of second conductive layers in the first direction;
and
a memory pillar extending in the first direction through the first conductive layers, the second conductive layers and the third conductive layers, wherein
the memory pillar has a first portion facing the first conductive layers and the second conductive layers, a second portion facing the third conductive layers, and a joint portion between the first and second portions in the first direction,
the first portion of the memory pillar narrows in width from a first end that is farthest from the joint portion in the first direction to a second end that is nearest the joint portion in the first direction, and
the second pitch is different from the first pitch.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/684,076Filed 1 Mar 2022
Priority: JP 2021-13887127 Aug 2021
Published: 2 Mar 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout

Family

US 12,745,390 B2Related patent
US 2023/0065666 A1This patent

From the US filing history. Foreign family members aren’t listed.

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