Scalable System on a Chip

A system comprising:

• a plurality of instances of an integrated circuit, the integrated circuit comprising:
• a plurality of processor cores;
• a plurality of graphics processing units;
• a plurality of peripheral devices distinct from the processor cores and graphics processing units;
• one or more memory controller circuits configured to interface with a system memory;
• an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
• and
• an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another one of the plurality of instances of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.