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US 2023/0058641 A1Published application
Analog-to-digital conversion with bit skipping functionality
AssigneeInternational Business Machines Corporation
InventorsMonodeep Kar, Ankur Agrawal, Mingu Kang, Kyu-hyoun Kim
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Abstract
Techniques for performing analog-to-digital conversion are disclosed. For example, a method performs an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.
Claims25
An apparatus comprising:
- at least one processor;
- and
- at least one memory including instruction code;
- the at least one memory and the instruction code being configured to, with the at least one processor, cause the apparatus at least to:
- perform an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.
2 more elements
A method, comprising the step of:
- performing an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit;
- wherein the method is executed by processing circuitry configured to execute instruction code.
An article of manufacture comprising a non-transitory computer-readable storage medium having embodied therein executable instruction code that when executed by a processor causes the processor to perform the step of:
- performing an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.
A system comprising:
- a dot-product summation computation unit configured to perform binary multiplication of first and second vectors;
- a successive approximation register analog-to-digital converter unit configured to convert an analog output of the dot-product summation computation unit to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits;
- and
- controller logic operatively coupled to the successive approximation register analog-to-digital converter unit, the controller logic being configured to determine values of the set of bits of the digital output based at least in part on a comparison of an output of the dot-product summation computation unit and a sequence of weighted binary codes;
- wherein the sequence of weighted binary codes starts from a given one of the one or more additional bits following the most significant bit.
2 more elements
A device comprising:
- dot-product summation circuitry configured to output a first signal, the first signal comprising a dot-product sum of binary multiplication of first and second vectors;
- and
- a successive approximation register analog-to-digital converter configured to perform conversion of the first signal output by the dot-product summation circuitry to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits;
- wherein the successive approximation register analog-to-digital converter comprises:
- successive approximation register controller circuitry configured to output a second signal;
- and
- comparator circuitry comprising a first input node coupled to the dot-product summation circuitry, a second input node coupled to the successive approximation register controller circuitry, and an output node configured to provide an output value based at least in part on a comparison of the first value output by the dot-product summation circuitry and the second value output by the successive approximation register controller circuitry;
- wherein the successive approximation register controller circuitry is configured to determine values of the set of bits of the digital output based at least in part on output values of the comparator circuitry produced as a sequence of weighted binary codes is output as the second signal;
- and
- wherein the sequence of weighted binary codes starts from a given one of the one or more additional bits following the most significant bit.
7 more elements
Dependencies are inferred from the claim text.