Reduced signaling interface method & apparatus
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
Claims8
An integrated circuit comprising:
- a functional circuit;
- an addressable test access port selection circuit having an address register configurable to store an address signal to enable test access;
- a first input/output pin configurable as an input or an output and coupled to the addressable test access port selection circuit, wherein the first input/output pin is configurable to input the address signal serially;
- a trace circuit coupled to the functional circuit and configured to generate trace data;
- and
- a second plurality of input/output pins, each pin configurable as an input or an output and coupled to the trace circuit, wherein the second plurality of input/output pins is configurable to output the trace data.
- a third plurality of input/output pins, each pin configurable as an input or an output and coupled to the functional circuit, wherein the third plurality of input/output pins is configurable to output data from the functional circuit.
Dependencies are inferred from the claim text.