US 2023/0058170 A1Published application

Memory device structure and forming method including reticle adjustment

AssigneeMicron Technology, Inc.

InventorYi Hu

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Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes memory cell strings having respective pillars extending through levels of first conductive materials interleaved with levels of first dielectric materials; conductive structures formed over the memory cell strings and extending through levels of second conductive materials interleaved with levels of second dielectric materials; dielectric structures located in respective trenches over the memory cell strings and dividing the levels of second conductive materials into portions that are electrically separated from each other; and the dielectric structures located such that the distance between two adjacent dielectric structures is different from the distance between two other adjacent dielectric structures.

Claims21

Dependent claims

An apparatus comprising:

levels of first conductive materials interleaved with levels of first dielectric materials;
memory cell strings including respective pillars extending through the levels of first conductive materials and the levels of first dielectric materials;
levels of second conductive materials interleaved with levels of second dielectric materials and located over the levels of first conductive materials and the levels of first dielectric materials;
conductive structures extending through the levels of second conductive materials and the levels of second dielectric materials and electrically coupled to the pillars, respectively;
dielectric structures located in respective trenches in the levels of second conductive materials and the levels of second dielectric materials and located over the levels of first conductive materials and the levels of first dielectric materials;
the dielectric structures dividing the levels of second conductive materials into portions that are electrically separated from each other, the portions including a first portion and a second portion;
the first portion located between and adjacent a first dielectric structure and a second dielectric structure of the dielectric structures, the second portion located between and adjacent the second dielectric structure and a third dielectric structure of the dielectric structures;
and
the first dielectric structure located at a first distance from the second dielectric structure, the second dielectric structure located at a second distance from the third dielectric structure, wherein the first distance is different from the second distance.

6 more elements

An apparatus comprising:

levels of first conductive materials interleaved with levels of first dielectric materials;
memory cell strings including respective pillars extending through the levels of first conductive materials and the levels of first dielectric materials;
levels of second conductive materials interleaved with levels of second dielectric materials and located over the levels of first conductive materials and the levels of first dielectric materials;
dielectric structures located in respective trenches in the levels of second conductive materials and the levels of second dielectric materials and located over the levels of first conductive materials and the levels of first dielectric materials;
the dielectric structures dividing the levels of second conductive materials into portions that are electrically separated from each other, the portions including a first portion, a second portion, and a third portion;
the first portion located between and adjacent a first dielectric structure and a second dielectric structure of the dielectric structures, the second portion located between and adjacent the second dielectric structure and a third dielectric structure of the dielectric structures, and the third portion located adjacent the third dielectric structure;
conductive structures extending through the levels of second conductive materials and the levels of second dielectric materials and electrically coupled to the pillars, respectively;
the conductive structures including first, second, and third conductive structures extending through the first, second, and third portions, respectively, of the levels of second conductive materials;
the first, second, and third conductive structures including a first conductive contact, a second conductive contact, and a third conductive contact, respectively;
and
a data line coupled to the first, second, and third conductive contacts;
and
the first conductive contact located at a first distance from the second conductive contact, the second conductive contact located at a second distance from the third conductive contact, wherein the first distance is different from the second distance.

10 more elements

A method comprising:

forming levels of first dielectric materials interleaved with levels of second dielectric materials;
forming memory cell strings including forming respective pillars of the memory cell strings through the levels of first dielectric materials and the levels of second dielectric materials;
forming levels of first additional dielectric materials interleaved with levels of second additional dielectric materials over the levels of first dielectric materials and the levels of second dielectric materials;
forming conductive structures through the levels of first additional dielectric materials and the levels of second additional dielectric materials, such that the conductive structures are in electrical contact with the pillars, respectively;
dividing the levels of first additional dielectric materials, the levels of second additional dielectric materials, the levels of first dielectric materials, and the levels of second dielectric materials into portions, each of the portions including a respective portion of the memory cell strings;
replacing the levels of first dielectric materials with respective levels of first conductive materials, and replacing the levels of first additional dielectric materials with respective levels of second conductive materials;
adjusting patterns on a reticle based on locations of the first conductive structures;
forming trenches based on the patterns on the reticle, the trenches formed through the levels of second additional dielectric materials and the levels of second conductive materials;
forming dielectric structures in the trenches;
and
forming conductive lines in electrical contact with the conductive structures.

8 more elements

A method comprising:

forming levels of first dielectric materials interleaved with levels of second dielectric materials;
forming memory cell strings including forming respective pillars of the memory cell strings through the levels of first dielectric materials and the levels of second dielectric materials;
forming levels of first additional dielectric materials interleaved with levels of second additional dielectric materials over the levels of first dielectric materials and the levels of second dielectric materials;
forming first conductive structures through the levels of first additional dielectric materials and the levels of second additional dielectric materials, such that the first conductive structures are in electrical contact with the pillars, respectively;
dividing the levels of first additional dielectric materials, the levels of second additional dielectric materials, the levels of first dielectric materials, and the levels of second dielectric materials into portions, each of the portions including a respective portion of the memory cell strings;
replacing the levels of first dielectric materials with respective levels of first conductive materials, and replacing the levels of first additional dielectric materials with respective levels of second conductive materials;
forming trenches through the levels of second additional dielectric materials and the levels of second conductive materials, and forming respective dielectric structures in the trenches;
adjusting patterns on a reticle based on locations of the first conductive structures;
forming second conductive structures based on the patterns on the reticle, the second conductive structures formed over and in electrical contact with the first conductive structures, respectively;
and
forming conductive lines in electrical contact with the second conductive structures.

8 more elements

A method comprising:

forming levels of first dielectric materials interleaved with levels of second dielectric materials;
forming memory cell strings including forming respective pillars of the memory cell strings through the levels of first dielectric materials and the levels of second dielectric materials;
forming levels of first additional dielectric materials interleaved with levels of second additional dielectric materials over the levels of first dielectric materials and the levels of second dielectric materials;
forming conductive structures through the levels of first additional dielectric materials and the levels of second additional dielectric materials, such that the conductive structures are in electrical contact with the pillars, respectively;
dividing the levels of first additional dielectric materials, the levels of second additional dielectric materials, the levels of first dielectric materials, and the levels of second dielectric materials into portions, each of the portions including a respective portion of the memory cell strings;
replacing the levels of first dielectric materials with respective levels of first conductive materials to form control gates for the memory cell strings;
replacing the levels of first additional dielectric materials with respective levels of second conductive materials;
forming dielectric structures through the levels of second additional dielectric materials and the levels of second conductive materials;
forming a staircase structure from respective portions of the control gates;
adjusting patterns on a reticle based on locations of the portions of the control gates;
forming conductive contacts using the reticle, the conductive contacts being in electrical contact with respective portions of the control gates;
and
forming conductive lines in electrical contact with the conductive structures.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/404,649Filed 17 Aug 2021
Published: 23 Feb 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10P 74/23
Testing or measuring during manufacture or treatment of wafers, substrates or devices: characterised by multiple measurements, corrections,…
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND

Family

US 12,745,606 B2Related patent
US 2023/0058170 A1This patent

From the US filing history. Foreign family members aren’t listed.

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