Modifying program and erase parameters for single-bit memory cells to improve single-bit/multi-bit hybrid ratio

An apparatus, comprising:

• a control circuit configured to connect to a set of memory cells in a block, the control circuit is configured to:
• determine whether a number of program-erase cycles for the block in a single bit per cell mode is below a first threshold;
• and
• erase the set of memory cells using an erase-verify voltage which is a function of whether the number of program-erase cycles for the block in the single bit per cell mode is below the first threshold, the erase-verify voltage is higher when the number of program-erase cycles for the block in the single bit per cell mode is below the first threshold than when the number of program-erase cycles for the block in the single bit per cell mode is above the first threshold;
• erase the set of memory cells with a modified initial erase pulse when the number of program-erase cycles for the block in the single bit per cell mode is below the first threshold;
• and
• erase the set of memory cells with a default initial erase pulse, greater than the modified initial erase pulse, when the number of program-erase cycles for the block in the single bit per cell mode is above the first threshold.