Semiconductor device including re-distribution pads disposed at different levels and a method of manufacturing the same

A semiconductor device, comprising:

• a chip body having a first metal pad and a second metal pad;
• a passivation layer on the chip body;
• a lower dielectric layer on the passivation layer;
• a first re-distribution pad on the lower dielectric layer;
• an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad;
• and
• a second re-distribution pad on the upper dielectric layer,
• wherein the first re-distribution pad includes:
• a first via portion vertically penetrating the lower dielectric layer to be coupled with the first metal pad;
• and
• a first extended portion extending from the first via portion in a first horizontal direction, and
• wherein the second re-distribution layer includes:
• a second via portion vertically penetrating the upper dielectric layer and the lower dielectric layer to be coupled with the second metal pad;
• and
• a second extended portion extending from the second via portion in the first horizontal direction.

A semiconductor device, comprising:

• a lower dielectric layer disposed on a chip body;
• a plurality of first re-distribution pads disposed on the lower dielectric layer;
• an upper dielectric layer disposed on the lower dielectric layer, the upper dielectric layer having grooves that expose the first re-distribution pads;
• and
• a plurality of second re-distribution pads disposed on the upper dielectric layer,
• wherein:
• the first re-distribution pads and the second re-distribution pads extend in parallel in a first horizontal direction, and
• the first re-distribution pads and the second re-distribution pads are alternately disposed in a second horizontal direction, the first horizontal direction and the second horizontal direction being perpendicular to each other.

A method of manufacturing a semiconductor device, comprising:

• preparing a chip body with a first metal pad and a second metal pad;
• forming a passivation layer on the chip body;
• forming a lower dielectric layer on the passivation layer;
• forming a first re-distribution pad on the lower dielectric layer;
• forming an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad;
• and
• forming a second re-distribution pad on the upper dielectric layer.