US 2023/0057441 A1 · MASKED TRAINING AND ANALYSIS WITH A MEMORY ARRAY

Abstract

Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

Claims20

Dependent claims

An apparatus, comprising:

a first pulse amplitude modulation (PAM) decoder coupled with a maximum transition avoidance (MTA) decoder of a memory device, the first PAM decoder configured to output a first data symbol of a data set;
a second PAM decoder coupled with the MTA decoder, the second PAM decoder configured to output a second data symbol of the data set;
and
a switching circuit coupled with an input node of the MTA decoder, the first PAM decoder, and the second PAM decoder.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/047,893Filed 19 Oct 2022

Priority

3 May 2021

Published

23 Feb 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification18 codes

G06F 3/0634
Configuration or reconfiguration of storage systems: by changing the state or mode of one or more devices
G11C 7/1084
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input buffers,…
G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/0679
Single storage device: non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Masked training and analysis with a memory array

Life of this patent

Masked training and analysis with a memory array

Life of this patent

Abstract

Claims20