Memory device for correcting pulse duty and memory system including the same

A memory system comprising:

• a memory device including a plurality of memory blocks and a primary pulse correction module;
• and
• a controller configured to transmit a control signal for controlling the memory device,
• wherein the primary pulse correction module includes:
• a reset signal generation circuit configured to generate a reset signal on the basis of the control signal;
• a primary pulse detection circuit configured to output a detection signal by detecting a primary pulse of the control signal on the basis of the reset signal;
• and
• a corrected primary pulse output circuit configured to correct the primary pulse on the basis of the detection signal.