Semiconductor structure and method for preparing same
AssigneeChangxin Memory Technologies, Inc.
InventorCHIH-CHENG LIU
Life of this patent
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Abstract
A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.
Claims20
A semiconductor structure, comprising:
- a substrate;
- a conductive pattern layer, arranged on the substrate;
- a support layer, covering the conductive pattern layer and provided with a via hole;
- and
- a re-distribution layer, arranged on the support layer;
- the re-distribution layer comprising:
- a test pad at least located in the via hole;
- the test pad comprising a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, wherein the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.
A method for preparing a semiconductor structure, comprising:
- providing a substrate, and forming a conductive pattern layer on the substrate;
- forming a support layer on the conductive pattern layer, and forming a via hole in the support layer;
- and
- forming a re-distribution layer on the support layer, wherein the re-distribution layer comprises a test pad that is at least located in the via hole, the test pad comprising a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and wherein the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.
Dependencies are inferred from the claim text.