US 2023/0056494 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorsWataru MORIYAMA, Hayato KONNO, Takao NAKAJIMA, Fumihiro KONO, Masaki FUJIU, Kiyoaki IWASA, Tadashi SOMEYA

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Abstract

A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

A semiconductor memory device comprising:

a substrate that includes a first region and a second region arranged in a first direction and a third region disposed between the first region and the second region;
a plurality of word lines extending in the first direction across the first region, the second region, and the third region, the plurality of word lines being arranged in a second direction intersecting with the first direction;
a first select gate line that is disposed in the first region and farther from the substrate than the plurality of word lines;
a second select gate line that is disposed in the first region and closer to the substrate than the plurality of word lines;
a first semiconductor layer disposed in the first region, the first semiconductor layer extending in the second direction and being opposed to the plurality of word lines, the first select gate line, and the second select gate line;
a first bit line extending in a third direction intersecting with the first direction and the second direction, the first bit line being disposed at a position overlapping with the first semiconductor layer viewed in the second direction;
a third select gate line that is disposed in the second region and farther from the substrate than the plurality of word lines;
a fourth select gate line that is disposed in the second region and closer to the substrate than the plurality of word lines;
a second semiconductor layer disposed in the second region, the second semiconductor layer extending in the second direction and being opposed to the plurality of word lines, the third select gate line, and the fourth select gate line;
a second bit line extending in the third direction, the second bit line being disposed at a position overlapping with the second semiconductor layer viewed in the second direction;
and
a word line contact electrode disposed in the third region, the word line contact electrode extending in the second direction and being connected to one of the plurality of word lines.

9 more elements

Facts

Application

17/695,529Filed 15 Mar 2022

Priority

JP 2021-13372118 Aug 2021

Published

23 Feb 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 16/16
Circuits for erasing electrically, e.g. erase voltage switching circuits: for erasing blocks, e.g. arrays, words, groups
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits

Abstract

Claims18