Low-latency forward error correction for high-speed serial links
AssigneeIntel Corporation
InventorDebendra Das Sharma
Life of this patent
Estimating the term…
Abstract
Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.
Claims19
An apparatus comprising:
- a port for transmitting data across a link, the link comprising multiple lanes;
- and
- a link coupled to the port, the port to:
- determine a data block to be transmitted across the link;
- determine a plurality of error correcting code symbols for forward error correction;
- interleave each of the plurality of error correcting code symbols across each lane of the multilane link to correspond with consecutive symbols of the data block;
- and
- transmit the data block comprising the interleaved plurality of error correcting code across the link.
A method comprising:
- determining a plurality of error correcting code symbols for forward error correction based on the size of the data block;
- interleaving each of the plurality of error correcting code symbols across each lane of the multilane link to correspond with consecutive symbols of the data block;
- and
- transmitting the data block comprising the interleaved plurality of error correcting code across the link.
An apparatus comprising:
- a port to receive data;
- and
- a link comprising multiple lanes coupled to the port,
- the port comprising hardware circuitry to:
- receive a data block from across the link;
- calculate row parity and check bits for the received data block using a parity-check matrix;
- compare the calculated row parity and check bits against row parity and check bits received in the data block, the data block comprising multiple error correcting code words interleaved among consecutive symbols of the data block;
- and
- correct errors based on the comparison of the calculated row parity and check bits against the received row parity and check bits received in the data block.
Dependencies are inferred from the claim text.