Processor core simulator including trace-based coherent cache driven memory traffic generator

A computer implemented method comprising:

• simulating at least one processor including a core element and at least one lower-level cache excluded from the core element;
• simulating a trace-based traffic generator that includes a plurality of modeled caches that model the at least one lower-level cache without modeling the core element, the simulated trace-based traffic generator configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic;
• and
• simulating a memory subsystem that is shared between the at least one simulated processor and the simulated trace-based traffic generator,
• wherein the simulated trace-based traffic generator performs a data exchange with the simulated memory subsystem based on the at least one workload trace, the data exchange impacting a measured performance of the at least one simulated processor.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:

• simulating at least one processor including a core element and at least one lower-level cache excluded from the core element;
• simulating a trace-based traffic generator that includes a plurality of modeled caches that model the at least one lower-level cache without modeling the core element, the simulated trace-based traffic generator configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic;
• and
• simulating a memory subsystem that is shared between the at least one simulated processor and the simulated trace-based traffic generator,
• wherein the simulated trace-based traffic generator performs a data exchange with the simulated memory subsystem based on the at least one workload trace, the data exchange impacting a measured performance of the at least one simulated processor.