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US 2023/0056044 A1Published application
Scalable System on a Chip
AssigneeApple Inc.
InventorsPer H. Hammarlund, Lior Zimet, James Vash, Gaurav Garg, Sergio Kolor, Harshavardhan Kaushikkar, Ramesh B. Gunna, Steven R. Hutsell
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Abstract
A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.
Claims30
A system, comprising:
- a plurality of processor cores;
- a plurality of graphics processing units;
- a plurality of peripheral devices distinct from the processor cores and graphics processing units;
- one or more memory controller circuits configured to interface with a system memory;
- and
- an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
- wherein the processor cores, graphics processing units, peripheral devices and memory controllers are configured to communicate via a unified memory architecture.
4 more elements
A system on a chip (SOC), comprising:
- a plurality of processor cores;
- a plurality of graphics processing units;
- a plurality of peripheral devices;
- one or more memory controller circuits;
- and
- an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
- wherein the processor cores, graphics processing units, peripheral devices and memory controllers are configured to communicate over the interconnect fabric via a unified memory architecture.
4 more elements
A method comprising:
- communicating, in a system on a chip (SOC), using a unified memory architecture over a communication fabric among a plurality of memory controllers, a plurality of processors, a plurality of peripheral circuits, wherein the unified memory architecture provides a common set of semantics for memory access by the processor cores, graphics processing units, and peripheral devices.
Dependencies are inferred from the claim text.