Drc test pattern generation method and apparatus, electronic device, and storage medium

An electronic device, comprising a memory and a processor,

• wherein the memory is configured to store a computer program executable by the processor,
• wherein when executing the computer program, the processor is configured to:
• receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries a number of correct patterns and a number of erroneous patterns;
• acquire layout design rule information and corresponding layer configuration information, wherein the layer configuration information comprises process layer configuration parameter information that is set according to a process type;
• parse parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generate formatted parameter information corresponding to the each rule according to the parameter information corresponding to the each rule, process layer configuration parameter information associated with the each rule, the number of correct patterns, and the number of erroneous patterns, respectively;
• and
• generate a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to the each rule according to the formatted parameter information corresponding to the each rule.

A nonvolatile computer-readable storage medium, having a computer program stored thereon, wherein when executed by a processor, the program is configured to:

• receive a DRC test pattern generation request, wherein the DRC test pattern generation request carries a number of correct patterns and a number of erroneous patterns;
• acquire layout design rule information and corresponding layer configuration information, wherein the layer configuration information comprises process layer configuration parameter information that is set according to a process type;
• parse parameter information corresponding to each rule in the layout design rule information and the process layer configuration parameter information in the layer configuration information, and generate formatted parameter information corresponding to the each rule according to the parameter information corresponding to the each rule, process layer configuration parameter information associated with the each rule, the number of correct patterns, and the number of erroneous patterns, respectively;
• and
• generate a corresponding number of correct patterns and a corresponding number of erroneous patterns corresponding to the each rule according to the formatted parameter information corresponding to the each rule.