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US 2023/0055458 A1Published application
Designing single event upset latches
AssigneeXilinx, Inc.
InventorsPierre MAILLARD, Betty LAU, Yanran CHEN, Jun LIU, Martin L. VOOGEL
Life of this patent
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Abstract
One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.
Claims20
An integrated circuit (IC), comprising:
- an inverter with an input and an output;
- a clock transmission gate coupled to the output of the inverter;
- and
- a plurality of storage cells, wherein the clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes, each of the plurality of nodes is spaced apart from other nodes of the plurality of nodes based on a minimum spacing.
1 more element
A method for designing an integrated circuit (IC) layout, comprising:
- determining a redundancy scheme for cell radiation tolerance for an IC layout, wherein the integrated circuit layout comprises a first IC component having a plurality of nodes;
- determining minimum spacing between the plurality of nodes for cell radiation tolerance;
- and
- arranging the plurality of nodes of the first component for the IC layout based on the determined minimum spacing and based on the redundancy scheme.
1 more element
An apparatus, comprising:
- at least one processor;
- and
- a memory coupled to the at least one processor, the memory comprising code executable by the at least one processor to cause the apparatus to:
- determine a redundancy scheme for cell radiation tolerance for an integrated (IC) layout, wherein the IC layout comprises a first IC component having a plurality of nodes;
- determine minimum spacing between the plurality of nodes for cell radiation tolerance;
- and
- arrange the plurality of nodes of the first component for the IC layout based on the determined minimum spacing and based on the redundancy scheme.
4 more elements
Dependencies are inferred from the claim text.