Loop execution in a reconfigurable compute fabric.

A reconfigurable compute fabric, comprising:

• a dispatch interface programmed to send a first asynchronous message to a first flow controller of a first synchronous flow, the first asynchronous message instructing the first flow controller to begin execution of a first-level loop and comprising an indication of a number of iterations of the first-level loop;
• multiple flow controllers;
• multiple compute elements, the multiple flow controllers and multiple compute elements being arranged into at least a first synchronous flow comprising a first flow controller and a first number of the multiple compute elements and a second synchronous flow comprising a second number of the multiple compute elements;
• the first synchronous flow being programmed to perform operations comprising:
• responsive to the first asynchronous message, sending a second asynchronous message to a second flow controller of a second synchronous flow, the second asynchronous message instructing the second flow controller to execute a second-level loop and comprising an indication of a number of iterations of the second-level loop;
• receiving, by the first flow controller, a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop;
• responsive to the third asynchronous message, sending a fourth asynchronous message to the second flow controller, the fourth asynchronous message instructing the second flow controller to execute the second-level loop;
• determining, by the first flow controller, that the number of iterations of the first-level loop have executed;
• and
• initiating a memory write writing to a memory at least one of a result of the first-level loop or a result of the second-level loop.

A machine-readable medium comprising instructions thereon that, when executed by a computer architecture, cause the computer architecture to perform operations comprising:

• sending, by a dispatch interface of the computer architecture, a first asynchronous message to a first flow controller of a computer architecture, the first asynchronous message instructing the first flow controller to begin execution of a first-level loop at a first synchronous flow of the computer architecture and comprising an indication of a number of iterations of the first-level loop, the first synchronous flow comprising the first flow controller and a first number of compute elements of the computer architecture;
• responsive to the first asynchronous message, sending, by the first synchronous flow, a second asynchronous message to a second flow controller of the computer architecture, the second asynchronous message instructing the second flow controller to execute a second-level loop at a second synchronous flow of the computer architecture and comprising an indication of a number of iterations of the second-level loop;
• receiving, by the first flow controller, a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop, the second synchronous flow comprising the second flow controller and a second number of compute elements of the computer architecture;
• responsive to the third asynchronous message, sending, by the first synchronous flow, a fourth asynchronous message to the second flow controller, the fourth asynchronous message instructing the second flow controller to execute the second-level loop;
• determining, by the first flow controller, that the number of iterations of the first-level loop have executed;
• and
• initiating, by the first flow controller, a memory write writing to a memory at least one of a result of the first-level loop or a result of the second-level loop.