Low-noise amplifier (lna) with high power supply rejection ratio (psrr)

A low-noise amplifier, comprising:

• a low-noise amplifier stage having a first gain element with an input for receiving an input signal, and an output for providing a first amplified signal, and at least one lowpass filter circuit each having an input coupled to a bias terminal and a first current conduction path coupled between a first power supply voltage terminal and said output of said first gain element;
• a bandpass and biasing stage having a second gain element with an input coupled to said output of said first gain element, and an output for providing a second amplified signal, and at least one cascode element having an input coupled to said bias terminal, and a second current conduction path coupled in series between said bias terminal and said output of said second gain element;
• and
• at least one bandpass stage coupled in series, each having a respective gain element with an input coupled to an output of a previous bandpass stage, and an output for providing a corresponding amplified signal, and at least one corresponding cascode element having an input coupled to said bias terminal, and a respective current conduction path coupled in series between said first power supply voltage terminal and said output of a corresponding previous gain element.

A method of amplifying an input signal to provide an output signal with a very high power-supply rejection ratio (PSRR), comprising:

• amplifying a radio-frequency (RF) input signal using a first gain element coupled between a first power supply voltage terminal and a second power supply voltage terminal and providing an amplified signal in response to said amplifying;
• and
• biasing said first gain element, said biasing comprising modulating a conductivity of at least one cascode transistor, and said biasing further comprising:
• generating a bias voltage at a bias terminal using a bias current;
• lowpass filtering said bias voltage to form a lowpass filtered bias voltage;
• and
• biasing a control electrode of each of said at least one cascode transistor using said lowpass filtered bias voltage.