Post error correction code registers for cache metadata

A method, comprising:

• reading metadata from a memory array included in an interface controller coupled with volatile memory and a non-volatile memory, the metadata comprising information for operating the volatile memory as a cache for the non-volatile memory;
• performing an error correction code (ECC) operation on the metadata based at least in part on reading the metadata from the memory array;
• writing, based at least in part on performing the ECC operation, the metadata to a register that is coupled with the memory array;
• and
• writing the metadata from the register to the memory array.

An apparatus, comprising:

• a non-volatile memory;
• a volatile memory configured to operate as a cache for the non-volatile memory;
• and
• an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller comprising:
• a static random access memory (SRAM) array configured to store metadata for operating the volatile memory as the cache;
• error correction code (ECC) logic coupled with the SRAM array and configured to perform an ECC operation on the metadata from the SRAM array;
• and
• a register, for a bank of the volatile memory, coupled with the ECC logic and configured to store metadata from the ECC logic, wherein the interface controller is configured to update the metadata in the register and communicate the metadata from the register to the SRAM array.