Semiconductor package

A semiconductor package, comprising:

• a package substrate;
• a redistribution layer on the package substrate;
• a connection substrate that connects the package substrate to the redistribution layer, the connection substrate having an opening that vertically penetrates the connection substrate;
• a first semiconductor chip in the opening of the connection substrate, a first active surface of the first semiconductor chip being in contact with the package substrate;
• a second semiconductor chip in the opening of the connection substrate, a second active surface of the second semiconductor chip being in contact with the redistribution layer;
• and
• a third semiconductor chip on the redistribution layer,
• wherein the redistribution layer includes
• a dielectric pattern;
• a first redistribution pad and a second redistribution pad that are on a top surface of the dielectric pattern;
• a first redistribution via that vertically penetrates the dielectric pattern to connect the first redistribution pad to a chip pad of the second semiconductor chip;
• and
• a protection layer on the top surface of the dielectric pattern, the protection layer covers the first redistribution pad and the second redistribution pad,
• wherein the third semiconductor chip is directly connected through a chip terminal to the second redistribution pad exposed on the protection layer, and
• wherein the first redistribution pad and the second redistribution pad are at a same level from the package substrate.

A semiconductor package, comprising:

• a package substrate;
• a first semiconductor chip on the package substrate;
• a redistribution layer on the first semiconductor chip;
• a second semiconductor chip mounted on a first surface of the redistribution layer;
• a third semiconductor chip mounted on a second surface of the redistribution layer;
• and
• a connection member between the package substrate and the redistribution layer and beside of the first semiconductor chip, the connection member connects the package substrate to the redistribution layer,
• wherein the redistribution layer includes a first redistribution pad and a second redistribution pad that are at a same level from the package substrate,
• wherein the second semiconductor chip is directly connected through a first terminal on the first redistribution pad,
• wherein the third semiconductor chip is directly connected through a second terminal on the second redistribution pad,
• wherein the redistribution layer includes a first region on which the first redistribution pad is provided and a second region on which the second redistribution pad is provided,
• wherein the second region vertically overlaps both of the second semiconductor chip and the third semiconductor chip, and
• wherein the first region is laterally spaced apart from the third semiconductor chip.