Systems and methods for stalling host processor
AssigneeDover Microsystems, Inc.
InventorsSteven Milburn, Gregory T. Sullivan
Life of this patent
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Abstract
Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.
Claims25
A method for stalling a host processor, the method comprising acts of:
- causing the host processor to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction;
- and
- preventing the host processor from completing the one or more selected transactions, to thereby stall the host processor.
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A method for stalling transactions on a first bus along a communication path between an upstream component and a downstream component, the method comprising acts of:
- causing the upstream component to initiate a transaction on a second bus, wherein the second bus is outside the communication path between the upstream component and the downstream component;
- and
- stalling the transaction on the second bus to thereby stall the upstream component.
A system comprising circuitry and/or one or more processors programmed by executable instructions, wherein the circuitry and/or the one or more programmed processors are configured to perform a method for stalling a host processor, the method comprising acts of:
- causing the host processor to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction;
- and
- preventing the host processor from completing the one or more selected transactions, to thereby stall the host processor.
Dependencies are inferred from the claim text.