Lateral persistence directory states

A system comprising:

• one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric, and a cache controller configured to perform:
• for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector;
• arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains;
• determining a first cache line to evict based on the chronology vector for the cache line;
• and
• determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:

• defining one or more processor units having a plurality of caches, wherein each processor unit comprises a processor having at least one cache from the plurality of caches, and wherein each of the one or more processor units are coupled together by an interconnect fabric;
• for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class in the one or more congruence classes comprises a chronology vector;
• arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains;
• determining a first cache line to evict based on the chronology vector for the first cache line;
• and
• determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

A computer-implemented method comprising:

• receiving a request to evict a first cache line from a first cache on a first microprocessor chip in a plurality of microprocessor chips in a processing drawer, the first cache line having a first set of lateral persistence bits tracking a scope for the first cache line;
• determining the scope of the first cache line;
• identifying a target cache having a saturation metric, wherein the target cache comprises a higher scope than the scope of the first cache line;
• and
• determining an action for the first cache line based on the saturation metric for the target cache and the scope of the first cache line.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:

• receiving a request to evict a first cache line from a first cache on a first microprocessor chip in a plurality of microprocessor chips in a processing drawer, the first cache line having a first set of lateral persistence bits tracking a scope for the first cache line;
• identifying a target cache having a saturation metric;
• determining the scope of the first cache line;
• and
• determining an action for the first cache line based on the saturation metric for the target cache and the scope of the first cache line.