Multi-gate transistors and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShahaji B. More, Cheng-Han Lee, Shih-Chieh Chang, Wan-Hsuan Hsieh, Chung-En Tsai, Chee-Wee Liu
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Abstract
The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.
Claims20
A semiconductor structure, comprising:
- a plurality of nanostructures disposed over a substrate, wherein each of the plurality of nanostructures comprises a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate;
- and
- a gate structure wrapping around each of the plurality of nanostructure.
A semiconductor structure, comprising:
- a first source/drain feature and a second source/drain feature disposed over a substrate;
- a plurality of channel members extending between the first source/drain feature and the second source/drain feature, wherein each of the plurality of channel members comprises a semiconductor layer sandwiched between two cap layers along a direction perpendicular to the substrate;
- and
- a gate structure wrapping around each of the plurality of channel members,
- wherein the gate structure is in direct contact with the semiconductor layer and the two cap layers of each of the plurality of channel members.
A method, comprising:
- depositing a buffer layer over a substrate;
- forming a stack on the buffer layer, wherein the stack comprises:
- a plurality of channel layers,
- a plurality of sacrificial layers interleaving the plurality of channel layers, and
- at least one cap layer disposed between each of the plurality of channel layers and an adjacent one of the plurality of sacrificial layers;
- forming a fin-shaped structure from the stack, the buffer layer and the substrate, the fin-shaped structure comprising a channel region and a source/drain region,
- forming a dummy gate stack over the channel region of the fin-shaped structure;
- depositing a gate spacer layer over the dummy gate stack;
- recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of channel layers and the plurality of sacrificial layers;
- selectively and partially recessing the plurality of sacrificial layers and a portion of the at least one cap layer to form a plurality of inner spacer recesses;
- forming a plurality of inner spacer features in the plurality of inner spacer recesses;
- forming a source/drain feature in the source/drain trench;
- removing the dummy gate stack;
- selectively removing the plurality of sacrificial layers to release the plurality of channel layers in the channel region as a plurality of channel members;
- and
- forming a gate structure around each of the plurality of channel members,
- wherein a composition of the at least one cap layer is different from a composition of the plurality of channel layers or a composition of the plurality of sacrificial layers.
Dependencies are inferred from the claim text.