Inferring future value for speculative branch resolution

A system comprising:

• a memory having computer readable instructions;
• and
• one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
• determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction;
• determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction;
• determining a predicted result of the compare instruction;
• completing the conditional branch instruction using the predicted result prior to executing the compare instruction;
• and
• writing a first instruction tag into a conditional register mapper;
• setting a first bit to one in the conditional register mapper based on the first instruction comprising a compare instruction;
• setting a second bit to zero in the conditional register matter based on the first instruction not being executed and written back.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:

• determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction;
• determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction;
• determining a predicted result of the compare instruction;
• completing the conditional branch instruction using the predicted result and
• writing a first instruction tag into a conditional register mapper;
• setting a first bit to one in the conditional register mapper based on the first instruction comprising a compare instruction;
• setting a second bit to zero in the conditional register matter based on the first instruction not being executed and written back.