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US 2023/0053795 A1Published application
Bit line pre-charge circuit and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChe-Ju Yeh, Yu-Hao Hsu, Hau-Tai Shieh, Cheng Lee
Life of this patent
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Abstract
A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.
Claims20
A method, comprising:
- when a switch circuit is in a first state, coupling an input terminal of a first clock signal generator to an external clock through the switch circuit and supplying an external clock signal generated by the external clock to the first clock signal generator and a second clock signal generator;
- and
- when the switch circuit is in a second state, coupling an output terminal of the second clock signal generator to the input terminal of first clock signal generator while continuing to supply the external clock signal to the second clock signal generator.
A bit line pre-charge circuit, comprising:
- a first clock signal generator comprising an output terminal;
- a second clock signal generator coupled to the first clock signal generator and comprising an input terminal;
- and
- a switch circuit comprising an output terminal coupled to the input terminal of the second clock signal generator, wherein:
- when the switch circuit is in a first state, the input terminal of the second clock signal generator is coupled to an external clock through the switch circuit, and
- when the switch circuit is in a second state, the output terminal of the first clock signal generator is coupled to the input terminal of the second clock signal generator through the switch circuit.
3 more elements
A bit line pre-charge circuit, comprising:
- a first clock signal generator configured to output a first clock signal, and
- a switch circuit comprising an output terminal configured to output the first clock signal when the switch circuit is in a first state or an external clock signal generated by an external clock when the switch circuit is in a second state, wherein:
- a timing of a first edge of a pulse of the first clock signal is a function of a second edge of the pulse of the first clock signal when the switch circuit is in the first state, and
- the timing of the first edge of the pulse of the first clock signal is a function of an edge of a pulse of the external clock signal when the switch circuit is in the second state.
1 more element
Dependencies are inferred from the claim text.