US 2023/0053693 A1Published application

3d synapse device stack, 3d stackable synapse array using the 3d synapse device stacks and method of fabricating the stack

AssigneeSeoul National University R&Db Foundation

InventorsJong-Ho LEE, Young-tak SEO, Soochang LEE, Seongbin OH, Jangsaeng KIM

Life of this patent

Estimating the term…

Loading patent…

Abstract

Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack. The 3D synapse device stack comprises: a body electrode disposed on a substrate in a vertical direction; a plurality of first insulating layers and third oxide layers alternately stacked on the outer circumferential surface of the body electrode; a plurality of semiconductor bodies disposed on an outer circumferential surface of the third oxide layer; a plurality of sources alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a first side surface of the body electrode; a plurality of drains alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a second side surface of the body electrode; a plurality of word lines alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a third side surface of the body electrode; and an insulator stack positioned between the word line and the semiconductor body. The semiconductor body, the source, the drain, the insulator stack and the word line located on the same layer on the outer peripheral surface of the body electrode constitute a synapse device or a part thereof. The synapse device stack may implement an AND-type or NOR-type synapse array.

Claims12

Dependent claims

A three-dimensional synapse device stack, which comprises:

a substrate having an upper surface formed of a first oxide layer;
a body electrode having a pillar shape, made of an electrically conductive material and dispoed on the substrate in a vertical direction;
a plurality of first insulating layers disposed on an outer circumferential surface of the body electrode;
a plurality of third oxide layers disposed on the outer circumferential surface of the body electrode and alternately stacked with the first insulating layers;
a plurality of semiconductor bodies disposed on an outer circumferential surface and the surface of the third oxide layers, made of semiconductor materials and electrically connected to the body electrode, and alternately stacked with the first insulating layers;
a plurality of sources disposed on an outer circumferential surface of the semiconductor bodies and alternately stacked with first insulating layers positioned on a first side surface of the body electrode;
a plurality of drains disposed on an outer circumferential surface of a semiconductor bodies and alternately stacked with the first insulating layers positioned on a second side surface of the body electrode opposite to the first side surface;
a source line electrode having a pillar shape, disposed on the substrate in a vertical direction and electrically connected to the plurality of sources;
a drain line electrode having a pillar shape, disposed on the substrate in a vertical direction and electrically connected to the plurality of drains;
a plurality of word lines disposed on an outer circumferential surface of the semiconductor bodies and alternately stacked with first insulating layers positioned on a third side surface of the body electrode;
and
a plurality of insulator stacks disposed between the word lines and the semiconductor bodies;
wherein the semiconductor body, the source, the drain, the insulator stack and the word line located on the same layer on the outer peripheral surface of the body electrode constitute a synapse device or a part thereof, and the synapse devices electrically isolated from each other by the first insulating layers and the third oxide layers are stacked to form a stack structure.

10 more elements

A method of manufacturing a three-dimensional synapse device stack comprising the following steps:

(a) forming a stacked structure by alternately depositing first insulating layers and second insulating layers on a substrate;
(b) etching predetermined regions of the stacked structure using a photolithography process to form a first etch hole, a second etch hole, a third etch hole, and a trench for stack isolation, and to the etched regions of the stacked structure depositing a passivation material and then planarizing the surface;
(c) selectively etching the passivation material filled in the first etch hole to expose the first etch hole, selectively etching a part of the second insulating layers from the surface of the first etch hole to be recessed, depositing a semiconductor material in the recssed regions to form semiconductor bodies;
(d) filling only the inside of the recessed regions where the semiconductor bodies are formed with an oxide material, and forming a body electrode made of a conductive material in the exposed region;
(e) selectively etching the passivation material filled in the second and third etch holes, selectively etching the second insulating layers from the surfaces of the second and third etch holes to be recessed, and depositing a highly doped semiconductor material in the recessed spaces and the second and the third etch holes to form a plurality of sources, a plurality of drains, a source line electrode connected to the sources, and a drain line electrode connected to the drains;
and
(f) selectively etching the passivation material filled in the trench for stack isolation, selectively etching the second insulating layers from the surface of the trench for stack isolation to be recessed, depositing sequentially an insulator stack and a conductive material on the surface of the recessed spaces, and then etching to form a plurality of word lines isolated electrically for each layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/888,772Filed 16 Aug 2022
Priority: 17 Aug 2021
Published: 23 Feb 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G06N 3/065
Using electronic means: analogue means
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits

Family

Application63/233,939Us provisional application · filed 17 Aug 2021
US 12,495,553 B2Related patent
US 2023/0053693 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key