Full Die and Partial Die Tape Outs from Common Design

A method comprising:

• defining, in a design database corresponding to an integrated circuit design, an area to be occupied by the integrated circuit design when fabricated on a semiconductor substrate;
• defining a chop line that demarcates the area into a first subarea and a second subarea, wherein a combination of the first subarea and the second subarea represents a full instance of the integrated circuit, and wherein the first subarea and a stub area represents a partial instance of the integrated circuit that includes fewer circuit components than the full instance;
• representing, in the design database, a physical location of a plurality of circuit components included in both the full instance and the partial instance of the integrated circuit in the first subarea, wherein a relative location of the plurality of circuit components within the first subarea and an interconnect of the plurality of circuit components within the first subarea is unchanged in the full instance and the partial instance;
• representing, in the design database, a physical location of another plurality of circuit components included in the full instance but excluded from the partial instance in the second subarea;
• defining, in the stub area in the design database, terminations for wires that would otherwise traverse the chop line between the first and second subareas, ensuring correct operation of the plurality of circuit components in the first subarea in the absence of the second subarea in the partial instance;
• producing a first data set for the full instance using the first subarea and the second subarea, the first data set defining the full instance for manufacturing the full instance;
• and
• producing a second data set for the partial instance using the first subarea and the stub area, the second data set defining the partial instance for manufacture of the partial instance.