Back to results
US 2023/0053595 A1Published application
Field effect transistor with multi-metal gate via and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Sung-Li WANG, Chih-Hao WANG
Life of this patent
Estimating the term…
Abstract
A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.
Claims20
A device, comprising:
- a substrate;
- a gate structure wrapping around a vertical stack of nanostructure semiconductor channels;
- a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels;
- and
- a gate via in contact with the first gate structure, including:
- a metal liner layer having a first flowability;
- and
- a metal fill layer having a second flowability higher than the first flowability.
5 more elements
A device comprising:
- a substrate;
- a first semiconductor channel over the substrate;
- a gate structure over and surrounding the semiconductor channel;
- a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel;
- a source/drain region abutting the second semiconductor channel;
- a source/drain contact over the source/drain region, formed of a first conductive material having first conductivity;
- a source/drain via in contact with the source/drain contact, formed of the first conductive material;
- and
- a gate via in contact with the gate structure, formed of at least one second conductive material having lower conductivity than the first conductive material.
6 more elements
A method, comprising:
- forming a gate structure over and surrounding nanostructure semiconductor channels over a substrate;
- forming a source/drain region over and in the substrate;
- forming a source/drain contact in contact with the source/drain region;
- forming a gate via by:
- forming a first opening exposing the gate structure;
- forming a metal liner layer in the first opening;
- and
- forming a first metal fill layer over the metal liner layer of a different material than the metal liner layer;
- and
- forming a source/drain via by:
- forming a second opening exposing the source/drain contact;
- and
- forming a second metal fill layer in the second opening of a different material than the first metal fill layer.
10 more elements
Dependencies are inferred from the claim text.