Processing system, related integrated circuit, device and method

A method for operating a processing system, the method comprising:

• programming, by a microprocessor during a Controller Area Network Flexible Data-Rate (CAN FD) Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode;
• generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame;
• storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory;
• activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface;
• and
• programming, by the microprocessor during a CAN FD Light data reception phase, the control register in order to activate a slave mode;
• enabling, by the microprocessor during the CAN FD Light data reception phase, a first hardware timer circuit and a second hardware timer circuit of the processing system in response to a first control signal so that a second DMA channel transfers packets of a given word size from a reception shift register of the SPI communication interface to the memory thereby sequentially transferring a reception CAN FD Light frame from the reception shift register to the memory;
• and
• reading, by the microprocessor during the CAN FD Light data reception phase, the reception CAN FD Light frame from the memory in response to the second control signal.

A processing system for managing a Controller Area Network Flexible Data-Rate (CAN FD) Light data transmission mode and/or a CAN FD Light data reception mode, wherein the processing system is connectable to a memory, the processing system comprising:

• a transmission terminal configured to provide a transmission signal;
• a reception terminal configured to receive a reception signal;
• a Serial Peripheral Interface (SPI) communication interface connected to the transmission terminal and the reception terminal, the SPI communication interface comprising:
• a control register configured to store data identifying a clock scaling factor and data identifying a mode of operation, the mode of operation indicating a master mode or a slave mode;
• a transmission shift register of a given word size configured to generate the transmission signal by sequentially providing a content of the transmission shift register in response to a first clock signal;
• a reception shift register of the given word size configured to sequentially add a logic level of the reception signal to a content of the reception shift register in response to a second clock signal;
• and
• a clock downscale circuit configured to receive an incoming clock signal and generate a downscaled clock signal by downscaling the incoming clock signal as a function of the clock scaling factor,
• wherein the SPI communication interface is configured to:
• provide, in the master mode, the downscaled clock signal as the first clock signal to the transmission shift register, and
• provide, in the slave mode, a clock signal received at a clock terminal as the second clock signal to the reception shift register;
• and
• a microprocessor configured to:
• when in the CAN FD Light data transmission mode,
• program the control register in order to activate the master mode,
• generate a transmission CAN FD Light frame,
• store the transmission CAN FD Light frame to the memory, and
• activate a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to the transmission shift register, and
• when in the CAN FD Light data reception mode,
• program the control register in order to activate the slave mode,
• in response to a first control signal, enable a first hardware timer circuit and a second hardware timer circuit so that a second DMA channel is configured to transfer packets of the given word size from the reception shift register to the memory, thereby sequentially transferring a reception CAN FD Light frame from the reception shift register to the memory, and
• in response to a second control signal, read the reception CAN FD Light frame from the memory.