Scalable System on a Chip

A system on a chip (SOC) integrated onto a semiconductor die, the SOC comprising:

• a plurality of processor cores;
• a plurality of graphics processing units;
• a plurality of peripheral devices;
• one or more memory controller circuits;
• and
• an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
• wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network comprises one or more characteristics to reduce latency compared to a second network of the at least two networks.

A system on a chip (SOC) integrated onto a semiconductor die, the SOC comprising:

• a plurality of processor cores;
• a plurality of graphics processing units;
• a plurality of peripheral devices;
• one or more memory controller circuits;
• and
• an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices;
• wherein the interconnect fabric comprises at least a first network and a second network, wherein the first network is physically and logically independent from the second network.