Apparatus and methods for producing stable clock signals based on a varying frequency source clock

A system on a chip (SoC) comprising:

• an oscillator configured to produce an oscillator signal at a first frequency;
• a first clock divider configured to:
• produce, based on the oscillator signal:
• a first clock signal at the first frequency;
• and
• a second clock signal at a second frequency being a division of the first frequency by an integer greater than 1;
• selectively provide the first clock signal as a first output clock signal when a scaling configuration signal has a first value;
• selectively provide the second clock signal as the first output clock signal when the scaling configuration signal has a second value;
• and
• produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal;
• a second clock divider configured to:
• produce a second output clock signal at a third frequency, the second output clock signal being based on the first output clock signal and the frequency indication signal, the third frequency being a division of the second frequency by an integer greater than or equal to 1;
• and
• a third clock divider configured to:
• produce, based on the second output clock signal, a third output clock signal at a fourth frequency being a division of the third frequency by an integer greater than 1.

A method for operation a system on a chip (SoC), the method comprising:

• producing, based on an oscillator signal at a first frequency, a first clock signal at the first frequency;
• producing, based on the oscillator signal, a second clock signal at a second frequency being a division of the first frequency by an integer greater than 1;
• selectively, based on a scaling configuration signal:
• providing the first clock signal as a first output clock signal when the scaling configuration signal has a first value;
• or
• providing the second clock signal as the first output clock signal when the scaling configuration signal has a second value;
• producing a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal;
• and
• producing, by a second clock divider, a second output clock signal at a third frequency, the second output clock signal being based on the first output clock signal and the frequency indication signal, the third frequency being a division of the second frequency by an integer greater than or equal to 1.