Detecting data bus drive faults

A method, comprising:

• applying, in response to a set of data pins being in an idle state, a first voltage to the set of data pins;
• outputting, by the set of data pins, a first signal based at least in part on applying the first voltage to the set of data pins;
• applying, in response to a pin associated with communicating error correction information being in the idle state, a second voltage to the pin, the second voltage being different than the first voltage;
• and
• outputting, by the pin, a second signal based at least in part on applying the second voltage to the pin, a validity of the first signal being indicated by the second signal.

A method, comprising:

• transmitting, to a memory device, a command associated with reading data stored at the memory device;
• detecting, based at least in part on transmitting the command and during a first time period associated with communicating data requested by the command, a set of signals at a set of data pins, wherein each signal of the set of signals comprises a first voltage level;
• detecting, based at least in part on transmitting the command and during a second time period associated with communicating error correction information for the data requested by the command, a signal at a pin associated with communicating the error correction information, wherein the signal comprises a second voltage level;
• determining the data associated with the set of signals is invalid based at least in part on a voltage of each signal of the set of signals being equivalent to the first voltage level for the first time period and a voltage of the signal being equivalent to the second voltage level for the second time period;
• and
• discarding the data based at least in part on determining the data is invalid.

An apparatus, comprising:

• a memory array comprising an array of memory cells that each comprise capacitive storage elements;
• and
• a circuit coupled with the memory array and configured to cause the apparatus to:
• apply, in response to a set of data pins being in an idle state, a first voltage to the set of data pins;
• output, by the set of data pins, a first signal based at least in part on the first voltage being applied to the set of data pins;
• apply, in response to a pin associated with communicating error correction information being in the idle state, a second voltage to the pin, the second voltage being different than the first voltage;
• and
• output, by the pin, a second signal based at least in part on the second voltage being applied to the pin, a validity of the first signal being indicated by the second signal.

An apparatus, comprising:

• a memory array comprising an array of memory cells that each comprise capacitive storage elements;
• and
• a circuit coupled with the memory array and configured to cause the apparatus to:
• transmit, to a memory device, a command associated with reading data stored at the memory device;
• detect, based at least in part on transmitting the command and during a first time period associated with communicating data requested by the command, a set of signals at a set of data pins, wherein each signal of the set of signals comprises a first voltage level;
• detect, based at least in part on transmitting the command and during a second time period associated with communicating error correction information for the data requested by the command, a signal at a pin associated with communicating the error correction information, wherein the signal comprises a second voltage level;
• determine the data associated with the set of signals is invalid based at least in part on a voltage of each signal of the set of signals being equivalent to the first voltage level for the first time period and a voltage of the signal being equivalent to the second voltage level for the second time period;
• and
• discard the data based at least in part on determining the data is invalid.