US 2023/0044462 A1 · Low Latency Network Device and Method for Treating Received Serial Data

Abstract

A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.

Claims20

Dependent claims

A low-latency network device for treating serial data received at a receiving data rate, the device comprising:

an oscillator generating a device-wide clock;
a receiving physical medium attachment (PMA) having an internal data width, the PMA being configured to:
receive the serial data,
deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and
output a parallelized sample stream;
a symbol timing synchronization module configured to:
receive the parallelized sample stream;
and
detect, from the parallelized sample stream, synchronized bit values corresponding to bit values of the received serial data;
and
a physical convergence sublayer (PCS) configured to:
receive the synchronized bit values;
and
delineate packets from the synchronized bit values, to provide packet-delineated parallelized data,
the receiving PMA, the symbol timing synchronization module and the PCS being all driven by the device-wide clock.

12 more elements

A method for processing serial data received at a receiving data rate, the method comprising:

deserializing the received serial data, through a receiving physical medium attachment (PMA), to output a parallelized sample stream, the deserializing being driven by a device-wide clock generated by an oscillator, and according to a word-width of the parallelized sample stream, whereby the parallelized sample stream is an oversampling of the received serial data, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data;
detecting, through a symbol timing synchronization module, from the parallelized sample stream, synchronized bit values corresponding to bit values of the received serial data;
and
delineating packet on the synchronized bit values, through a physical convergence sublayer (PCS), to provide packet-delineated parallelized data,
wherein the receiving PMA, the symbol timing synchronization module and the PCS being all driven by the device-wide clock.

2 more elements

Dependencies are inferred from the claim text.

Low Latency Network Device and Method for Treating Received Serial Data

Life of this patent

Low Latency Network Device and Method for Treating Received Serial Data

Life of this patent

Abstract

Claims20