Ferroelectric memory circuit and reading method thereof

A memory cell circuit (100), comprising:

• a set of memory cells (102), a first control line connecting the memory cells (102) of the set of memory cells (102);
• a set of second control lines, each second control being connected to a respective memory cell (102) of the set of memory cells (102);
• wherein a memory state (102s) of each of the memory cell (102) is switchable between a first memory state and a second memory state, the memory cell (102) further configured to output an electrical current (101) via the first control line in response to receiving a readout voltage (103) via one of the second control lines;
• a sense circuit (104) configured to output an output voltage (105) based on the electrical current (101) output by the memory cell (102), wherein the output voltage (105) represents, whether the memory state (102s) is the first memory state or the second memory state.