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US 2022/0413852 A1Published application
Processor embedded streaming buffer
AssigneeIntel Corporation
InventorJoseph Williams
Life of this patent
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Abstract
Techniques are disclosed for the use of local buffers integrated into the execution units of a vector processor architecture. The use of local buffers results in less communication across the interconnection network implemented by vector processors, and increases interconnection network bandwidth, increases the speed of computations, and decreases power usage.
Claims20
A vector processing unit, comprising:
- a buffer configured to store a set of vector data samples that are retrieved from one or more vector registers;
- and
- vector processing circuitry configured to:
- for a first vector processor instruction that is executed during a first one of a plurality of clock cycles, perform a first vector processing operation using a first portion of the stored set of vector data samples,
- for a second vector processor instruction that is executed during a second one of the plurality of clock cycles, perform a second vector processing operation using a second portion of the stored set of vector data samples,
- wherein a predetermined number of the first portion of the stored set of vector data samples used to perform the first vector processing operation are the same as the second portion of the stored set of vector data samples used to perform the second vector processing operation.
3 more elements
A system on a chip (SoC), comprising:
- a plurality of vector registers;
- and
- a plurality of vector processing units, each one of the plurality of vector processing unit comprising:
- a buffer configured to store a set of vector data samples that are retrieved from one or more of the plurality of vector registers;
- and
- vector processing circuitry configured to:
- for a first vector processor instruction that is executed during a first one of a plurality of clock cycles, perform a first vector processing operation using a first portion of the stored set of vector data samples, and
- for a second vector processor instruction that is executed during a second one of the plurality of clock cycles, perform a second vector processing operation using a second portion of the stored set of vector data samples,
- wherein a predetermined number of the first portion of the stored set of vector data samples used to perform the first vector processing operation are the same as the second portion of the stored set of vector data samples used to perform the second vector processing operation.
6 more elements
Dependencies are inferred from the claim text.