Ecc decoders having low latency

An error correction code (ECC) decoder comprising:

• a syndrome calculation block configured to receive a codeword from a memory medium to calculate and output a syndrome;
• a fast path controller configured to receive and store the codeword and configured to output the codeword when no error is detected from a result of the calculation of the syndrome;
• a key equation solver (KES) block configured to include a plurality of KES-stages, wherein a first KES-stage of the plurality of KES-stages is configured to calculate and output an error location/magnitude polynomial of the syndrome outputted from the syndrome calculation block, each of a second to last KES-stages of the plurality of KES-stages is configured to receive the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation, and the additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial;
• a Chien-search and errata-evaluator (CSEE) block configured to find a solution of the additionally calculated error location/magnitude polynomial to correct an error of the codeword;
• an uncorrectable error detector (UED) configured to perform a logical operation of output data of the CSEE block and the codeword stored in the fast path controller to discriminate whether the codeword is corrected and to output data;
• and
• a multiplexer configured to output data having an earlier input point in time out of data corresponding to the codeword outputted from the fast path controller and the data outputted from the UED as final ECC decoded data.