Structures and methods of identifying unprogrammed bits for one-time-programmable-memory (otpm)

A structure, comprising:

• a comparison circuit which comprises a hardware memory controller which:
• identifies whether at least one bit of a first predetermined address for at least one twin-cell one-time-programmable memory (OTPM) has been programmed and whether at least one bit of a second predetermined address for the at least one twin-cell OTPM has been programmed based on a first read operation and a second read operation,
• checks an error correction circuit (ECC) flag bit of the at least one twin-cell OTPM to identify whether the at least one bit of the first predetermined address for the at least one twin-cell OTPM has been programmed;
• checks another ECC flag bit of the at least one twin-cell OTPM to identify whether the at least one bit of the second predetermined address for the at least one twin-cell OTPM has been programmed;
• and
• an OR gate which receives the ECC flag bit and the other ECC flag bit and outputs a block usage flag output (BUF).

A method, comprising:

• identifying whether at least one bit of an address for at least one twin-cell one-time-programmable memory (OTPM) has been programmed based on at least one read operation;
• checking an error correction circuit (ECC) flag bit of the at least one twin-cell OTPM to identify whether the at least one bit of the address for the at least one twin-cell OTPM has been programmed;
• checking another ECC flag bit of the at least one twin-cell OTPM to identify whether another bit of another address for the at least one twin-cell OTPM has been programmed;
• and
• receiving the ECC flag bit and the other ECC flag bit and outputs a block usage flag output (BUF).