Error sampler circuit
AssigneeTexas Instruments Incorporated
InventorsAbishek MANIAN, Nithin Sathisan PODUVAL, Roland Nii Ofei RIBEIRO
Life of this patent
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Abstract
An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
Claims20
An error sampler circuit, comprising:
- a differential input voltage input;
- a differential reference voltage input;
- a master latch circuit including:
- a slicer circuit including:
- a first input coupled to the differential input voltage input;
- a second input coupled to the differential reference voltage input;
- a differential output;
- and
- a slave latch circuit comprising:
- a differential input coupled to the differential output of the slicer circuit.
An error sampler circuit, comprising:
- a master latch circuit comprising:
- a slicer circuit configured to compare an input voltage to a reference voltage in a first phase of a clock signal;
- a first latch circuit coupled to the slicer circuit, and configured to latch an output of the slicer circuit in a second phase of the clock signal;
- a slave latch circuit coupled to the master latch circuit, and comprising:
- a comparator configured to compare a first output signal and a second output signal of the master latch circuit in the second phase of the clock signal;
- and
- a second latch circuit coupled to the comparator, and configured to latch an output of the comparator in the first phase of the clock signal.
An equalizer circuit, comprising:
- a decision feedback equalizer (DFE) circuit having a first output and a second output;
- a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to the DFE circuit;
- and
- an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit configured to:
- generate a first difference signal as a difference of the first output and a first reference signal;
- and
- generate a second difference signal as a difference of the second output and a second reference signal.
Dependencies are inferred from the claim text.