Microcontroller circuit, corresponding device, system and method of operation

A device, comprising a circuit, the circuit comprising:

• a first memory and a second memory;
• a processor coupled to the first memory and the second memory, the processor configured to:
• generate an output sequence comprising binary values encoding an outgoing Controller Area Network (CAN) frame according to a CAN protocol,
• process the output sequence to detect a sequence of ordered pulse-width modulated (PWM) periods, each PWM period comprising a first portion having a dominant state and a second portion having a recessive state, each PWM period having a respective total duration and a respective duty-cycle value,
• store a set of ordered first values indicative of a first parameter of the PWM periods in the sequence of ordered PWM periods in the first memory, and
• store a set of ordered second values indicative of a second parameter of the PWM periods in the sequence of ordered PWM periods in the second memory, wherein the first parameter and the second parameter define a shape of the PWM periods;
• and
• a CAN transceiver couplable to a CAN bus, wherein an output pin of the circuit is configured to drive the CAN transceiver to transmit over the CAN bus outgoing CAN frames encoded according to a CAN protocol.

A method, comprising:

• generating an output sequence of binary values encoding an outgoing CAN frame according to a CAN protocol;
• processing the output sequence of binary values to detect a sequence of ordered PWM periods, each PWM period comprising a first portion having a dominant state and a second portion having a recessive state, each PWM period having a respective total duration and a respective duty-cycle value;
• storing into a first memory a set of ordered first values indicative of a first parameter of the PWM periods in the sequence of ordered PWM periods;
• storing into a second memory bank a set of ordered second values indicative of a second parameter of the PWM periods in the sequence of ordered PWM periods, wherein the first parameter and the second parameter define a shape of the PWM periods;
• reading from the first memory and storing into a first register a value indicative of the first parameter of a current PWM period in the sequence of ordered PWM periods;
• increasing an internal count number of a counter circuit and resetting the internal count number of the counter circuit as a function of the value stored in the first register;
• reading from the first memory and storing into the first register a subsequent value indicative of the first parameter of a subsequent PWM period in the sequence of ordered PWM periods as a function of the value stored in the first register;
• reading from the second memory and storing into a second register a value indicative of the second parameter of the current PWM period;
• comparing the internal count number of the counter circuit to the value stored into the second register;
• driving an output pin to a dominant value or to a recessive value as a function of the comparing the internal count number of the counter circuit to the value stored into the second register, wherein the output pin provides an output PWM signal comprising the sequence of ordered PWM periods;
• and
• reading from the second memory and storing into the second register a subsequent value indicative of the second parameter of a subsequent PWM period in the sequence of ordered PWM periods in response to the internal count number of the counter circuit reaching the value stored into the second register or in response to the internal count number of the counter circuit reaching the value stored into the first register.