Pipelined forward error correction for vector signaling code channel

An apparatus comprising:

• a deserialization buffer configured to sequentially receive a plurality of data symbols, and to store each data symbol as a set of bits in a corresponding deserialization buffer location defined by a unique symbol position index;
• a forward error correction (FEC) circuit configured to:
• generate a first syndrome value from a first pair of multi-bit check words generated by performing bitwise XOR operations on the plurality of data symbols, the first syndrome value corresponding to a bit-error mask of a data symbol having an error;
• generate a second syndrome value from a second pair multi-bit check words generated by performing bitwise XOR operations on modulo-multiplied data symbols, each data symbol modulo-multiplied by the unique symbol position index, the second syndrome value corresponding to a modulo-multiplication of the bit-error mask with the unique symbol position index of the data symbol having the error;
• and
• calculate the symbol position index of the data symbol having the error by dividing the second syndrome value by the bit-error mask;
• and
• the deserialization buffer configured to generate a corrected set of output bits by applying the bit-error mask to the stored set of bits in the deserialization buffer location identified by the symbol position index of the data symbol having the error.