Superconducting integrated circuit design method based on placement and routing by different-layer jtls

A superconducting integrated circuit design method based on placement and routing by different-layer Josephson transmission lines (JTLs), comprising the following steps:

• step 1:
• cutting a bias line at a cell data interface of a cell library, and reserving a position of a via;
• step 2:
• placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram;
• step 3:
• connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer;
• and
• step 4:
• performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not at the same layer as the logic cell layer,
• wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells, and a JTL at an upper layer is connected to the cell data interface at a lower layer by using the via.