Trap circuits for use with differential capacitively-coupled resonant clock networks

A superconducting integrated circuit comprising:

• a resonant dock network capacitively-coupled to:
• (1) a first superconducting circuit comprising a first Josephson junction and a second Josephson junction, and (2) a second superconducting circuit comprising a third Josephson junction and a fourth Josephson junction;
• a first trap circuit coupled between the first Josephson junction and the resonant dock network, wherein the first trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and the third Josephson junction;
• and
• a second trap circuit coupled between the second Josephson junction and the resonant dock network, wherein the second trap circuit is configured to attenuate any signals generated by a triggering of the second Josephson junction to reduce crosstalk between the second Josephson junction and the fourth Josephson junction.

A superconducting integrated circuit comprising:

• a first superconducting circuit comprising:
• (1) a first Josephson junction coupled via a first capacitor to a first clock line, wherein the first capacitor is configured to receive a first alternating current (AC) clock signal having a first phase via the first clock line and couple a first bias current to the first Josephson junction, and (2) a second Josephson junction coupled via a second capacitor to a second dock line, wherein the second capacitor is configured to receive a second AC clock signal having a second phase, opposite to the first phase, via the second clock line and couple a second bias current to the second Josephson junction;
• a second superconducting circuit comprising:
• (1) a third Josephson junction coupled via a third capacitor to the first dock line, wherein the third capacitor is configured to receive the first AC clock signal having the first phase via the first clock line and couple a third bias current to the third Josephson junction, and (2) a fourth Josephson junction coupled via a fourth capacitor to the second clock line, wherein the fourth capacitor is configured to receive the second AC clock signal having the second phase via the second clock line and couple a fourth bias current to the second Josephson junction;
• a first trap circuit coupled between the first capacitor and the first Josephson junction, wherein the first trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and the third Josephson junction;
• and
• a second trap circuit coupled between the second capacitor and the second Josephson junction, wherein the second trap circuit is configured to attenuate any signals generated by a triggering of the second Josephson junction to reduce crosstalk between the second Josephson junction and the fourth Josephson junction.